1. Field of the Invention
The present invention relates to integrated circuit devices generally and more particularly to an output buffer having improved transient suppression.
2. Description of the Prior Art
A transient (spike or bounce) problem has been associated with certain high speed, high drive, CMOS, integrated circuit type output buffers. More specifically, when the state of an output buffer is switched, transients are developed across stray inductances in the buffer ground and power (V.sub.cc) paths. These transients are coupled to the outputs of other output buffers which share the same ground and power paths.
For example, consider the pair of prior art type output buffers illustrated in FIG. 1 of the drawing generally designated by the numbers 10 (on the left side of the drawing) and 10' (on the right), respectively. Buffer 10 is shown to employ a P-channel, field effect transistor (FET), which is designated 12 (in the center of the drawing), and an N-channel, field effect transistor, designated 14. Transistors 12 and 14 are connected in what is referred to herein as a (P-channel over N-channel) totem pole configuration. More specifically, the gate of transistor 12 is coupled by a line 20 and a pair of inverters 22 and 24 to the output of a 2-input NAND gate 26. The inputs of gate 26 are connected, one to a line 28 to receive a buffer 10 enabling signal and the other to a line 30 to receive a data input signal. The source of transistors 12 is connected to a line 40; and, the drain of the transistor (12) is connected to a line 50, upon which buffer 10 develops a data output signal.
The gate of transistor 14 is coupled by a line 60 and another inverter 62 to the output of another 2-input NAND gate 64. One of the inputs of gate 64 is coupled by still another inverter 66 to line 30; and, the other input of the gate is connected to line 28. The drain of transistor 14 is connected to a line 50; and, the source of the transistor is connected to a line 70.
Output buffer 10' is similar to output buffer 10. (For clarity, in the drawing, corresponding parts are similarly numbered, the buffer 10' part numbers additionally having a prime.)
The sources of transistors 12 and 12' are directly connected to receive a power supply potential (V.sub.cc); and, the sources of transistors 14 and 14' are directly connected to receive a circuit ground potential. However, there are stray inductances associated with the connections, attributable, in part, to the chip metalization, to the wire bonding, and to the lead frame. (The stray inductances pose a particular problem with devices which are of the series that is commonly designated 7400 and which are packaged in dual in-line packages (DIPs) in which the ground and power pins are located at the extreme ends of the package.)
For purposes of illustration, the stray inductances are represented by discrete inductors. Thus, in the drawing, line 40 is shown coupled by an inductor 80 (representing the stray inductances in the power path) to a line 82 to receive the power supply potential; and, line 70 is shown coupled by an inductor 84 (representing the stray inductances in the ground path) to a line 86 to receive the circuit ground potential.
The capacitive reactance of the output buffer 10 load is represented in the drawing by a discrete capacitor 90 connected between lines 50 and 86.
First, assume that output buffer 10 is in the state in which transistor 12 is "on" and transistor 14 is "off". In this state, a "high" logic level potential is developed on line 50 and across capacitor 90. Also, assume that output buffer 10' is in the state in which transistor 12' is "off" and transistor 14' is "on" developing a "low" logic level potential on line 50'.
Next, assume that the state of output buffer 10 is switched so as to turn transistor 12 "off" and transistor 14 "on". When transistor 14 is turned "on", the potential developed across capacitor 90 is coupled by transistor 14 across inductor 84. As a consequence, a transient is developed across inductor 84. Since transistor 14' (of output buffer 10') is "on", the transient is coupled by transistor 14' to line 50'. (A similar transient is developed on line 50' when output buffer 10' is held in the state in which transistor 12' is "on" and transistor 14' is "off" while the state of output buffer 10 is switched so as turn transistor 14 "off" and transistor 12 "on".)
The transient problem is primarily associated with high speed, high drive, CMOS, integrated circuit type output devices. With those devices of the 7400 series that are designated 74XXX, 74HXXX, 74SXXX, and 74LSXXX, the transient turns "off" the bipolar transistor equivalent of (FET) transistor 14' before the (bipolar) transistor couples an appreciable amount of the transient to the output of the output buffer. Also, with those devices of the 7400 series that are designated 74HCXXX and 74HCTXXX, the equivalent of transistors 12 and 14 and their drivers are not strong enough to develop an appreciable transient level across the equivalent of inductors 80 and 84. However, as the transistor channel length is decreased (to less than two micron (one millionth of a meter) and the transistor channel width is increased, a transient of appreciable level is developed across the equivalent of inductor 84 and coupled to the equivalent of line 50'. A transient having a rise time of less than one nanosecond and a level in excess of three volts has been observed across the equivalent of inductor 84 when seven of eight output buffers (of an octal buffer) are simultaneously switched.
For a additional information on the transient problem, the reader is directed to the articles which appeared on pages 29 and 30 of the Aug. 7, 1986 issue and on pages 81 and 82 of the Sept. 18, 1986 issue of Electronics.